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Freescale Semiconductor Technical Data
Document Number: MC33889 Rev. 11.0, 12/2006
System Basis Chip with Low Speed Fault Tolerant CAN Interface
An SBC device is a monolithic IC combining many functions repeatedly found in standard microcontroller-based systems, e.g., protection, diagnostics, communication, power, etc. The 33889 is an SBC having fully protected, fixed 5.0 V low drop-out regulator, with current limit, over-temperature pre-warning and reset. An output drive with sense input is also provided to implement a second 5.0 V regulator using an external PNP. The 33889 has Normal, Standby, Stop and Sleep modes; an internally switched high-side power supply output with two wake-up inputs; programmable timeout or window watchdog, Interrupt, Reset, SPI input control, and a lowspeed fault tolerant CAN transceiver, compatible with CAN 2.0 A and B protocols for module-to-module communications. The combination is an economical solution for power management, high-speed communication, and control in MCU-based systems. Features * VDD1: 5.0 V low drop voltage regulator, current limitation, overtemperature detection, monitoring and reset function with total current capability 200 mA * V2: tracking function of VDD1 regulator; control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply * Four operational modes * Low standby current consumption in Stop and Sleep modes * Built-in low speed 125 kbps fault tolerant CAN physical interface. * External high voltage wake-up input, associated with HS1 VBAT switch * 150 mA output current capability for HS1 VBAT switch allowing drive of external switches pull-up resistors or relays * Pb-Free Packaging Designated by Suffix Code EG
33889
SYSTEM BASIS CHIP
DW SUFFIX EG SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42345B 28-PIN SOICW
ORDERING INFORMATION
Device MC33889BDW/R2 MCZ33889BEG/R2 -40C to 125C MC33889DDW/R2 *MCZ33889DEG/R2 28 SOICW Temperature Range (TA) Package
*Recommended for new designs
33889
5.0 V VDD1 GND VSUP V2CTRL V2 HS1 L0 L1 WDOG RTH CANH CANL RTL
VPWR V2
MCU
CS SCLK MOSI MISO SPI
RST INT CS SCLK MOSI MISO TXD RXD
Local Module Supply Wake-Up Inputs Safe Circuits Twisted Pair
CAN Bus
Figure 1. 33889 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations Between the 33889D and 33889B Versions (1)
Device Part Number Parameters Differential Receiver, Recessive To Dominant Threshold (By Definition, VDIFF = VCANH-VCANL) Symbol Trait Min VDIFF1 Typ Max Differential Receiver, Dominant To Recessive Threshold (Bus Failures 1, 2, 5) Min VDIFF2 Typ Max CANH Output Current (VCANH = 0; TX = 0.0) ICANH Min Typ Max CANL Output Current (VCANL = 14 V; TX = 0.0) ICANL Min Typ Max Detection threshold for Short circuit to Battery voltage loop time Tx to Rx, no bus failure, ISO configuration loop time Tx to Rx, with bus failure, ISO configuration Vcanh tLOOPRD tLOOPRD-F max max max MC33889B(2) 3.2 V 2.6 V 2.1 V 3.2 V 2.6 V 2.1 V 50 mA 75 mA 110 mA 50 mA 90 mA 135 mA Vsup/2 + 5V N/A N/A N/A min typ max T2SPI timing DEVICE BEHAVIOR CANH or CANL open wire recovery principle Rx behavior in TermVbat mode Reference MC33889B: on page 33 after 4 non consecutive pulses after 4 consecutive pulses T2spi min N/A 30 N/A not specified, 25us spec applied MC33889D(2) 3.5 V 3.0 V 2.5 V 3.5 V 3.0 V 2.5 V 50 mA 100 mA 130 mA 50 mA 140 mA 170 mA Vsup/2 + 4.55V 1.5us 1.9us 3.6us 8 16 30 25us
loop time Tx to Rx, with bus failure and +-1.5V gnd shift, tLOOPRD/DR-F+GS 5 node network, ISO configuration Minimum Dominant time for Wake up on CANL or CANH (Tem Vbat mode) tWAKE
Reference MC33889D: on page Rx recessive, no pulse Rx recessive, dominant pulse to signal bus 34 traffic
Notes 1. This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B). 2. The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated onto individual lines.
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Analog Integrated Circuit Device Data Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
33889 Internal Block Diagram
V2CTRL V2 VDD1
VSUP
Dual Voltage Regulator VSUP Voltage Monitor VDD1 Voltage Monitor HS1 Control Oscillator
HS1 L0 L1 Programmable Wake-Up Inputs
INT Interrupt Watchdog Reset Mode Control TX WDOG RST
CS SCLK MOSI MISO GND V2 SPI Interface VSUP Fault Tolerant CAN Transceiver
RX RTH CAN H CAN L RTL
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PIN CONNECTIONS
PIN CONNECTIONS
RX TX VDD1 RST INT GND GND GND GND V2CTRL VSUP HS1 L0 L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
WDOG CS MOSI MISO SCLK GND GND GND GND CANL CANH RTL RTH V2
Figure 2. 33889 Pin Connections Table 2. Pin Definitions A functional description of each pin can be found in the Functional pin description section page 24.
Pin 1 2 3 Pin Name
RX
Pin Function Output Input Power Output
Formal Name Receiver Data Transmitter Data Voltage Regulator One
Definition CAN bus receive data output pin CAN bus receive data input pin 5.0 V pin is a 2% low drop voltage regulator for to the microcontroller supply. This is the device reset output pin whose main function is to reset the MCU. This output is asserted LOW when an enabled interrupt condition occurs. These device ground pins are internally connected to the package lead frame to provide a 33889-to-PCB thermal path. Output drive source for the V2 regulator connected to the external series pass transistor. Supply input pin.
TX
VDD1
4
RST
Output
Reset
5
INT
Output
Interrupt
6 -9, 20 - 23 10
GND
Ground
Ground
V2CTRL
Output
Voltage Source 2 Control
11
VSUP
Power Input
Voltage Supply
12 13 - 14 15
HS1
L0, L1
Output Input Input
High-Side Output Level 0 - 1 Inputs Voltage Regulator Two
Output of the internal high-side switch. Inputs from external switches or from logic circuitry. 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply. Pin for connection of the bus termination resistor to CANH. Pin for connection of the bus termination resistor to CANL. CAN high output pin. CAN low output pin. Clock input pin for the Serial Peripheral Interface (SPI).
V2
16 17 18 19 24
RTH RTL
CANH
Output Output Output Output Input
RTH RTL CAN High CAN Low System Clock
CANL
SCLK
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
Table 2. Pin Definitions (continued) A functional description of each pin can be found in the Functional pin description section page 24.
Pin 25 Pin Name MISO Pin Function Output Formal Name Master In/Slave Out Definition SPI data sent to the MCU by the 33889. When CSLOW is HIGH, the pin is in the high impedance state. SPI data received by the 33889. The CSLOW input pin is used with the SPI bus to select the 33889. When the CSLOW is asserted LOW, the 33889 is the selected device of the SPI bus. The WDOG output pin is asserted LOW if the software watchdog is not correctly triggered.
26 27
MOSI CS
Input Input
Master Out/Slave In Chip Select
28
WDOG
Output
Watchdog
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Supply Voltage at VSUP Continuous voltage Transient voltage (Load dump) Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WDOG, INT) Output current VDD1 HS1 Voltage Output Current L0, L1 DC Input voltage DC Input current Transient input voltage (according to ISO7637 specification) and with external component per Figure 3. DC voltage at V2 (V2INT) DC Voltage On Pins CANH, CANL Transient Voltage At Pins CANH, CANL 0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms Transient Voltage On Pins CANH, CANL (Coupled Through 1.0 nF Capacitor) DC Voltage On Pins RTH, RTL Transient Voltage At Pins RTH, RTL 0.0 < V2-INT < 5.5 V; VSUP = 0.0; T < 500 ms VWU IWU VTRWU V2INT VBUS VCANH/VCANL VTR VRTL, VRTH VRTH/VRTL -0.3 to 40 -2.0 to 2.0 +-100 V mA V V I -0.2 to VSUP +0.3 Internally Limited V A VLOG VSUP -0.3 to 27 40 -0.3 to VDD1 +0.3 V V Symbol Max Unit
I
Internally Limited
mA
0 to 5.25 -20 to +27 -40 to +40
V V V
-150 to +100 -0.3 to +27V -0.3 to +40
V V V
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ESD voltage (HBM 100 pF, 1.5 k) (3) CANL, CANH, HS1, L0, L1 RTH, RTL All other pins ESD voltage (Machine Model) All pins, MC33889B (3) (4) ESD voltage (CDM) All pins, MC33889D (4) Pins 1,14,15, & 28 All other pins RTH, RTL Termination Resistance THERMAL RATINGS Junction Temperature Storage Temperature Ambient Temperature (for info only) Thermal resistance junction to gnd pin (5) TJ TS TA RTHJ/P -40 to 150 -55 to 165 -40 to 125 20 C C C C/W RT VESD-MM VESD-CDM 750 500 500 to 16000 ohms Symbol VESDH 4.0 3.0 2.0 200 V V Max Unit kV
Notes: 3. Testing done in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 ), Machine Model (CZAP=200 pF, RZAP=0 ). 4. ESD machine model (MM) is for MC33889B only. MM is now replaced by CDM (Charged Discharged model). 5. Gnd pins 6,7,8,9,20, 21, 22, 23.
1nF LX 10 k
Transient Pulse Generator (note) Gnd
Gnd
Note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.
Figure 3. Transient test pulse for L0 and L1 inputs
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics . Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description INPUT PIN (VSUP) Nominal DC Voltage range Extended DC Voltage range 1 Reduced functionality
(6)
Symbol
Min
Typ
Max
Unit
VSUP VSUP-EX1
5.5 4.5
-
18 5.5
V V
Extended DC Voltage range 2 (8) Input Voltage during Load Dump Load dump situation Input Voltage during jump start Jump start situation Supply Current in Sleep Mode (7) VDD1 & V2 off, VSUP 12 V, oscillator running Supply Current in Sleep Mode (7) VDD1 & V2 off, VSUP 12 V, oscillator not running Supply current in sleep mode (7) VDD1 & V2 off, VSUP = 18 V, oscillator running Supply Current in Stand-by Mode (7),(9) Iout at VDD1 = 40 mA, CAN recessive state or disabled Supply Current in Normal Mode (7) Iout at VDD1 = 40 mA, CAN recessive state or disabled Supply Current in Stop mode (7),(9) I out VDD1 < 2.0 mA, VDD1 on (11), VSUP 12 V, oscillator running (10) Supply Current in Stop mode (7),(9) Iout VDD1 < 2.0 mA, VDD1 on not running (10) Supply Current in Stop mode (7),(9) Iout VDD1 < 2.0 mA, VDD1 on (11), VSUP = 18 V, oscillator running (10)
(11) (10) (10)
VSUP-EX2 VSUPLD
18 -
-
27 40
V V
VSUPJS
-
-
27
V
ISUP (SLEEP1) ISUP (SLEEP2) ISUP (SLEEP3) ISUP(STDBY)
-
95
130
A
-
55
90
A
-
170
270
A
-
42
45
mA
ISUP(NORM)
-
42.5
45
mA
ISUP (STOP1)
-
120
150
A
ISUP VSUP 12V, oscillator (STOP2)
-
80
110
A
ISUP (STOP3)
-
200
285
A
Notes 6. VDD1 > 4.0 V, reset high, if RSTTH-2 selected and IOUT VDD1 reduced, logic pin high level reduced, device is functional. 7. 8. 9. 10. 11. Current measured at VSUP pin. Device is fully functional. All modes available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 and L1 inputs operating, SPI read write operation. Over temperature may occur. Measured in worst case condition with 5.0 V at V2 pin (V2 pin tied to VDD1). Oscillator running means "Forced Wake-Up" or "Cyclic Sense" or "Software Watchdog" timer activated. Software Watchdog is available in stop mode only. VDD1 is ON with 2.0 mA typical output current capability.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description Supply Fail Flag internal threshold Supply Fail Flag hysteresis (12) Battery fall early warning threshold In normal & standby mode Battery fall early warning hysteresis In normal & standby mode OUTPUT PIN (VDD1) (13) VDD1 Output Voltage IDD1 from 2.0 to 200mA 5.5 V < VSUP < 27 V 4.5 V < VSUP < 5.5 V Drop Voltage VSUP > VDDOUT IDD1 = 200 mA Drop Voltage VSUP > VDDOUT, limited output current IDD1 = 50 mA 4.5 V < VSUP < 27 V IDD1 Output Current Internally limited VDD1 Output Voltage in stop mode Iout < 2.0 mA IDD1 stop output current to wake-up SBC Default value after reset.
(14) (12)
Symbol VTHRESH VDETHYST BFEW
Min 1.5 5.8
Typ 3.0 1.0 6.1
Max 4.0 6.4
Unit V V V
BFEWH
0.1
0.2
0.3
V
VDD1OUT 4.9 4.0 VDD1DROP 5.0 0.2 5.1 0.5
V
V
VDD1DP2
-
0.1
0.25
V
IDD1
200
270
350
mA
VDDSTOP
4.75
5.00
5.25
V
IDD1S-WU1
2.0
3.5
6.0
mA
IDD1 stop output current to wake-up SBC (14) IDD1 over current wake deglitcher (with IDD1S-WU1 selected) (12) IDD1 over current wake deglitcher (with IDD1S-WU2 selected) (12) Thermal Shutdown Normal or standby mode Over temperature pre warning VDDTEMP bit set Temperature Threshold difference
IDD1S-WU2 IDD1-DGIT11
10 40
14 55
18 75
mA s
IDD1-DGIT2
-
150
-
s
TSD
160
-
190
C
TPW
130
-
160
C
TSD-TPW
20
-
40
C
Notes 12. Guaranteed by design 13. IDD1 is the total regulator output current. VDD specification with external capacitor C 22F and ESR < 1O ohm. 14. Selectable by SPI
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description Reset threshold 1 Default value after reset. Reset threshold 2 (15) Reset duration VDD1 range for Reset Active Reset Delay Time Measured at 50% of reset signal. Line Regulation 9.0 V < VSUP < 18, IDD = 10 mA Line Regulation 5.5 V < VSUP < 27 V, IDD = 10 mA Load Regulation 1 mA < IIDD < 200 mA Thermal stability VSUP = 13.5 V, I = 100 mA V2 REGULATOR (V2) (17) V2 Output Voltage I2 from 2.0 to 200 mA 5.5 V < VSUP < 27 V I2 output current (for information only) Depending on the external ballast transistor V2 CTRL sink current capability V2LOW flag threshold Internal V2 Supply Current (CAN and SBC in Normal Mode). TX = 5.0 V, CAN in Recessive State Internal V2 Supply Current (CAN and SBC in Normal Mode). TX = 0.0 V, No Load, CAN in Dominant State Internal V2 Supply Current (CAN in Receive Only Mode, SBC in Normal mode). VSUP = 12 V Internal V2 Supply Current (CAN in Bus TermVbat mode, SBC in normal mode), VSUP = 12 V I2CTRL V2LTH IV2RS IV2DS IV2R IV2BT 10 3.75 3.8 4.0 5.6 4.25 6.8 mA V mA I2 200 mA V2 0.99 1.0 1.01 VDD1 THERMS 5.0 mV LD 25 75 mV LR2 10 25 mV
(16) (15)
Symbol VRST-TH1
Min 4.5
Typ 4.6
Max 4.7
Unit V
VRST-TH2 RESET-DUR VDD tD
4.1 0.85 1.0 5.0
4.2 1.0 -
4.3 2.0 20
V ms V s
LR1
-
5.0
25
mV
4.0
5.8
7.0
mA A A
80
120
35
60
Notes 15. Selectable by SPI 16. Guaranteed by design 17. V2 TRACKING VOLTAGE REGULATOR - V2 specification with external capacitor - option 1: C 22 F and ESR < 10 ohm. Using a resistor of 2 kohm or less between the base and emitter of the external PNP is recommended. - option2: 1.0 F < C < 22 F and ESR < 10 ohm. In this case depending on the ballast transistor gain an additional resistor and capacitor network between emitter and base of PNP ballast transistor might be required. Refer to Freescale application information or contact your local technical support. - option 3: 10uF < C < 22uF ESR > 0.2 ohms: a resistor of 2 kohm or less is required between the base and emitter of the external PNP. 33889
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description LOGIC OUTPUT PINS (MISO) Low Level Output Voltage IOUT = 1.5 mA High Level Output Voltage IOUT = -250 A Tri-state MISO Leakage Current 0.0 V < Vmiso < VDD LOGIC INPUT PINS (MOSI, SCLK, CS) High Level Input Voltage Low Level Input Voltage Input Current on CS VI = 4.0 V VI = 1.0 V Low Level Input Current CS VI = 1.0 V MOSI, SCLK Input Current 0.0 < VIN < VDD RESET PIN (RST) High Level Output current 0.0 < Vout < 0.7 VDD Low Level Output Voltage (I0 = 1.5 mA) 5.5 v < VSUP < 27 V 1.0 V < VDD1 Reset pull down current WATCHDOG PIN (WDOG) Low Level Output Voltage (I0 = 1.5 mA) 5.5 V < VSUP < 27 V High Level Output Voltage (I0 = -250 A) INTERRUPT PIN (INT) Low Level Output Voltage (I0 = 1.5 mA) High Level Output Voltage (I0 = -250 A) HIGH-SIDE OUTPUT PIN (HS1) RDSON at Tj = 25C, and IOUT -150 mA VSUP>9V RDSON25 2.5 Ohms VOL VOH 0.0 VDD1 -0.9 0.9 VDD1 V V VOH VDD1 -0.9 VDD1 V VOL 0.0 0.9 V IPDW VOL 0.0 0.0 2.3 0.9 0.9 5.0 mA V IOH -350 -250 -150 A IIN -10 10 A IIH IIL IIL -100 -20 A VIH VIL 0.7VDD1 -0.3 -100 VDD1+0.3V 0.3 VDD1 -20 V A IHZ -2.0 +2.0 A VOH VDD1-0.9 V VOL 1.0 V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description RDSON at Tj = 125C, and IOUT -150 mA VSUP > 9.0 V RDSON at Tj = 125C, and IOUT -120 mA 5.5 V < VSUP < 9.0 V Output current limitation Over temperature Shutdown Leakage current Output Clamp Voltage at IOUT = -1.0 mA no inductive load drive capability INPUT PINS (L0 AND L1) L0 Negative Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V L0 Positive Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V L1 Negative Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V L1 Positive Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18V 18 V < VSUP < 27 V Hysteresis 5.5 V < VSUP < 27 V Input current -0.2 V < VIN < 40 V CAN MODULE SPECIFICATION (TX, RX, CANH, CANL, RTH, AND RTL) DC Voltage On Pins TX, RX DC voltage at V2 (V2INT) DC Voltage On Pins CANH, CANL VLOGIC V2INT VBUS -0.3 0.0 -20 VDD1 + 0.3 5.25 +27 V V V IIN -10 10 A VHYST VTH1P 2.7 3.0 3.5 0.6 3.3 4.0 4.2 1.0 3.8 4.7 4.8 1.3 V VTH1N 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.7 3.8 V VTH0P 2.2 2.5 2.5 2.75 3.4 3.5 4.0 4.0 4.1 V VTH0N 1.7 2.0 2.0 2.0 2.4 2.5 3.0 3.0 3.1 V V
(18)
Symbol RDSON125
Min -
Typ -
Max 5.0
Unit Ohms
RDON125-2
-
4.0
5.5
Ohms
ILIM OVT ILEAK VCL
160 155 -1.5
-
500 190 10 -0.3
mA C A V
Notes 18. Refer to HS1 negative maximum rating voltage limitation of -0.2V.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description Transient Voltage At Pins CANH, CANL 0.0 < V2-INT < 5.5 V; VSUP 0.0; T < 500 ms Transient Voltage On Pins CANH, CANL (Coupled Through 1.0 nF Capacitor) Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode) MC33889B Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode) MC33889D DC Voltage On Pins RTH, RTL Transient Voltage At Pins RTH, RTL 0.0 < V2-INT < 5.5 V; VSUP 0.0; T < 500 ms TRANSMITTER DATA PIN (TX) High Level Input Voltage Low Level Input Voltage TX High Level Input Current (VI = 4.0 V) TX Low Level Input Current (VI = 1.0 V) RECEIVE DATA PIN (RX) High Level Output Voltage RX (I0 = -250 A) Low Level Output Voltage (I0 = 1.5 mA) CAN HIGH AND CAN LOW PINS (CANH, CANL) Differential Receiver, Recessive To Dominant Threshold (By Definition, VDIFF = VCANH-VCANL) For 33889D For 33889B Differential Receiver, Dominant To Recessive Threshold (Bus Failures 1, 2, 5) For 33889D For 33889B CANH Recessive Output Voltage TX = 5.0 V; R(RTH) < 4.0 k CANL Recessive Output Voltage TX = 5.0 V; R(RTL) < 4.0 k VCANL V2-INT - 0.2 V VCANH VDIFF2 -3.5 -3.2 -3.0 -2.6 -2.5 -2.1 0.2 V -3.5 -3.2 -3.0 -2.6 -2.5 -2.1 V VDIFF1 V VOH VOL V2-INT - 0.9 0.0 V2-INT 0.9 V V VIH VIL ITXH ITXL 0.7*V2 -0.3 -100 -100 -50 -50 V2+0.3V 0.3 * V2 -25 -25 V V A A VTR VCANH VCANH VRTL, VRTH VRTH/VRTL -150 100 V Symbol VCANH/VCANL Min -40 Typ Max 40 Unit V
VSUP/2+3 VSUP/2+3 -0.3 -0.3
VSUP/2+5 VSUP/ 2+4.55 +27 40
V
V
V V
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description CANH Output Voltage, Dominant TX = 0.0 V; ICANH = -40 mA; Normal Operating Mode (19) CANL Output Voltage, Dominant TX = 0.0 V; ICANL = 40 mA; Normal Operating Mode (19) CANH Output Current (VCANH = 0; TX = 0.0) For 33889D For 33889B CANL Output Current (VCANL = 14 V; TX = 0.0) For 33889D For 33889B Detection Threshold For Short-circuit To Battery Voltage (Normal Mode) Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode), MC33889B Detection Threshold For Short-circuit To Battery Voltage (Term VBAT Mode), MC33889D CANH Output Current (Term VBAT Mode; VCANH = 12 V, Failure3) CANL Output Current (Term VBAT Mode; VCANL = 0.0 V; VBAT = 12 V, Failure 4) CANL Wake-Up Voltage Threshold CANH Wake-Up Voltage Threshold Wake-Up Threshold Difference (Hysteresis) VWAKE,L VWAKE,H VWAKELVWAKEH VSE, CANH VSE, CANL ICANL,PU ICANH,PD RDIFF VCOM CCANH CCANL DCCAN tCSD 150 160 2.5 1.2 0.2 3.0 2.0 3.9 2.7 V V V VCANH, VCANL ICANL 50 50 7.3 140 90 7.9 170 135 8.9 V ICANH 50 50 100 75 130 110 mA mA VCANL 1.4 V Symbol VCANH Min V2 - 1.4 Typ Max Unit V
VcanH
Vsup/2+3
Vsup/2+5 Vsup/ 2+4.55 5.0 10
V
VcanH ICANH ICANL
Vsup/2+3
V A A
0.0
2.0
CANH Single Ended Receiver Threshold (Failures 4, 6, 7) CANL Single Ended Receiver Threshold (Failures 3, 8) CANL Pull Up Current (Normal Mode) CANH Pull Down Current (Normal Mode) Receiver Differential Input Impedance CANH / CANL Differential Receiver Common Mode Voltage Range CANH To Ground Capacitance CANL To Ground Capacitance CCANL to CCANH Capacitor Difference CAN Driver Thermal Shutdown
(20)
1.5 2.8 45 45 100 -10
1.85 3.05 75 75
2.15 3.4 90 90 300 10 50 50 10
V V A A kohm V pF pF pF C
Notes 19. For MC33889B, after 128 pulses on TX and no bus failure. 20. Guaranteed by design
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued). Characteristics noted under conditions - VSUP From 5.5 V to 18 V and TJ from -40C to 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Description BUS TERMINATION PINS (RTH, RTL) RTL to V2 Switch On Resistance (IOUT < -10 mA; Normal Operating Mode) RTL to BAT Switch Series Resistance (term VBAT Mode) RTH To Ground Switch On Resistance (IOUT < 10 mA; Normal Operating Mode) RRTL RRTH 8.0 10 12.5 30 20 90 kohm ohm RRTL 10 30 90 ohms Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40C to 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Conditions DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO) SPI operation frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 220 pF) MISO Fall Time (CL = 220 pF) Time from Falling or Rising Edges of CS to: - MISO Low Impedance - MISO High Impedance Time from Rising Edge of SCLK to MISO Data Valid 0.2 V1 SO 0.8 V1, CL = 200 pF Delay between CS low to high transition (at end of SPI stop command) and Stop or sleep mode activation (21) detected by V2 off Interrupt low level duration SBC in stop mode Internal oscillator frequency All modes except Sleep and Stop Notes 21. Guaranteed by design
(21)
Symbol
Min
Typ
Max
Unit
FREQ tPCLK tWSCLKH tWSCLKL tlLEAD
250 125 125 100
50
4.0 -
MHz ns ns ns ns
tLAG tSISU tSIH tRSO tfSO
100 40 40 -
50 25 25 25 25 -
50 50
ns ns ns ns ns ns
tSOEN tSODIS tVALID -
50 50 50 ns
TCS-STOP
18
-
34
s
TINT
7.0
10
13
s
OSC-F1
-
100
-
kHz
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40C to 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Conditions Internal low power oscillator frequency Sleep and Stop modes Watchdog period 1 Normal and standby modes Watchdog period 2 Normal and standby modes Watchdog period 3 Normal and standby modes Watchdog period 4 Normal and standby modes Watchdog period accuracy Normal and standby modes Normal request mode timeout Normal request mode Watchdog period 1 - stop Stop mode Watchdog period 2- stop Stop mode Watchdog period 3 - stop Stop mode Watchdog period 4 - stop Stop mode Stop mode watchdog period accuracy Stop mode Cyclic sense/FWU timing 1 Sleep and stop modes Cyclic sense/FWU timing 2 Sleep and stop modes Notes 22. Guaranteed by design CSFWU2 6.47 9.25 12 ms CSFWU1 3.22 4.6 5.98 ms F2ACC -30 30 % WD4STOP 245 350 455 ms WD3STOP 70 100 130 ms WD2STOP 31.5 45 58.5 ms WD1STOP 6.82 9.75 12.7 ms NRTOUT 308 350 392 ms F1ACC -12 12 % WD4 308 350 392 ms WD3 88 100 112 ms WD2 39.6 45 50.4 ms
(22)
Symbol OSC-F2
Min -
Typ 100
Max -
Unit kHz
WD1
8.58
9.75
10.92
ms
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40C to 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Conditions Cyclic sense/FWU timing 3 Sleep and stop modes Cyclic sense/FWU timing 4 Sleep and stop modes Cyclic sense/FWU timing 5 Sleep and stop modes Cyclic sense/FWU timing 6 Sleep and stop modes Cyclic sense/FWU timing 7 Sleep and stop modes Cyclic sense/FWU timing 8 Sleep and stop modes Cyclic sense On time in sleep and stop modes Cyclic sense/FWU timing accuracy in sleep and stop mode Delay between SPI command and HS1 turn on (23) Normal or standby mode, VSUP > 9.0 V Delay between SPI command and HS1 turn off (23) Normal or standby mode, VSUP > 9.0 V Delay between SPI and V2 turn on (23) Standby mode Delay between SPI and V2 turn off (23) Normal modes Delay between Normal Request and Normal mode, after W/D trigger command Normal request mode Notes 23. State Machine Timing - Delay starts at rising edge of CS (end of SPI command) and start of Turn on or Turn off of HS1 or V2. tS-NR2N 15 35 70 s tS-V2OFF 9.0 25 s tS-V2ON 9.0 25 s tS-HSOFF 22 s tS-HSON 22 s tACC -30 +30 % tON 200 300 400 s CSFWU8 271 388 504 ms CSFWU7 134 191 248 ms CSFWU6 66.8 95.5 124 ms CSFWU5 51.8 74 96.2 ms CSFWU4 25.9 37 48.1 ms Symbol CSFWU3 Min 12.9 Typ 18.5 Max 24 Unit ms
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40C to 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Conditions Delay between SPI and "CAN normal mode" SBC Normal mode
(24)
Symbol tS-CANN
Min -
Typ -
Max 10
Unit s
Delay between SPI and "CAN sleep mode" SBC Normal mode
(24)
tS-CANS
-
-
10
s
Delay between CS wake-up (CS low to high) and SBC normal request mode (VDD1 on & reset high) SBC in stop mode Delay between CS wake-up (CS low to high) and first accepted SPI command SBC in stop mode Delay between INT pulse and 1st SPI command accepted In stop mode after wake-up Delay between two SPI messages addressing the same register For 33889D only
tW-CS
15
40
90
s
tW-SPI
90
-
-
s
tS-1STSPI
20
-
-
s
t2SPI 25 -
s
INPUT PINS (L0 AND L1) Wake-up Filter Time (enable/disable option on L0 input) (If filter enabled) PIN AC CHARACTERISTICS (CANH, CANL, RX, TX) CANL and CANH Slew Rates (25% to 75% CAN signal). (25) Recessive to Dominant state Dominant to Recessive state Propagation Delay TX to RX Low. -40C < T 25C.
(26)
tWUF
8.0
20
38
s
tSLDR 2.0 2.0 8.0 9.0
V/s
tONRX 1.2 1.1 tOFFRX 1.8 1.6 1.8 2.2
s
TX to RX Low. 25C < T < 125C. (26) Propagation Delay TX to RX High. (26)
s
Notes 24. Guaranteed by design 25. Dominant to recessive slew rate is dependant upon the bus load characteristics. 26. AC Characteristics measured according to schematic Figure 4
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40C to 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Conditions Loop time Tx to Rx, no bus failure, MC33889D only ((27), Figure 5) (ISO ICT test series 10) Tx high to low transition (dominant edge) Tx low to high transition (recessive edge) Symbol tLOOPRD 1.15 1.45 tLOOPRD-F tLOOPRD/DR-F+GS 1.9 1.9 3.6 s 1.5 1.5 s Min Typ Max Unit s
Loop time Tx to Rx, with bus failure, MC33889D only ((27), Figure 6) (ISO ICT test series 10) Tx high to low transition (dominant edge) Tx low to high transition (recessive edge)
Loop time Tx to Rx, with bus failure and +-1.5V gnd shift, 5 nodes network, MC33889D,((28), Figure 7, ISO ICT tests series 11) Min. Dominant Time For Wake-up On CANL or CANH (Term Vbat; VSUP = 12V) Guaranteed by design. MC33889B MC33889D Failure 3 Detection Time (Normal Mode) Failure 3 Recovery Time (Normal Mode) Failure 6 Detection Time (Normal Mode) Failure 6 Recovery Time (Normal Mode) Failure 4, 7 Detection Time (Normal Mode) Failure 4, 7 Recovery Time (Normal Mode) Failure 3a, 8 Detection Time (Normal Mode) Failure 3a, 8 Recovery Time (Normal Mode) Failure 4, 7 Detection Time, (Term VBAT; VSUP = 12 V) Failure 4, 7 Recovery Time (Term VBAT; VSUP = 12 V) Failure 3 Detection Time (Term VBAT; VSUP = 12 V) Failure 3 Recovery Time (Term VBAT; VSUP = 12 V) Failure 3a, 8Detection Time (Term VBAT; VSUP = 12 V) Failure 3a, 8 Recovery Time (Term VBAT; VSUP = 12 V)
tWAKE 30 8.0 tDF3 tDR3 tDF6 tDR6 tDF47 tDR47 tDF8 tTDR8 tDR47 tDR47 tDR3 tDR3 tDR8 tDR8 50 150 0.75 10 0.75 0.75 0.8 10 16 30 160 200 200 1.5 30 1.7 1.5 1.2 1.92 3.84 1.92 2.3 1.2 500 1000 4.0 60 4.0 4.0 8.0 30 80
s
s s s s ms s ms ms ms ms ms ms ms ms
Notes 27. AC characteristic according to ISO11898-3, tested per figure 5 and 6. Guaranteed by design, room temperature only. 28. AC characteristic according to ISO11898-3, tested per figure 7. Max reported is the typical measurement under the worst condition (gnd shift, dominant/recessive edge, at source or destination node. ref to ISO test specification). Guaranteed by design, room temperature only. 33889
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) VSUP From 5.5 V to 18 V, V2INT from 4.75 to 5.25 V and TJ from -40C to 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Conditions Edge Count Difference Between CANH and CANL for Failures 1, 2, 5 Detection (Failure bit set, Normal Mode) Edge Count Difference Between CANH And CANL For Failures 1, 2, 5 Recovery (Normal Mode) TX Permanent Dominant Timer Disable Time (Normal Mode And Failure Mode) TX Permanent Dominant Timer Enable Time (Normal Mode And Failure Mode) Symbol ECDF Min Typ 3 Max Unit
ECDR
3
tTX,D
0.75
4.0
ms
tTX,E
10
60
s
VDD
RtL
5V
R
CANL
C
Tx CANL
500
RcanL
1nF
C
CANH
R = 100ohms C = 1nF
MC33889D Rx CANH RtH
500 RcanH
1nF
R
C
RcanL = RcanH = 125 ohms
Figure 4. Test Circuit for AC Characteristics
Vbat
RtL Tx CANL
Figure 5. ISO loop time without bus failure
500
Bus Failure Generator (*)
RcanL
1nF
MC33889D Rx CANH RtH
500
RcanH
1nF
RcanL = RcanH = 125 ohms except for failure CANH short to CANL (Rcanl = 1M ohms)
(*) List of failure CANL short to gnd, Vdd, Vbat CANHshort to gnd, Vdd, Vbat CANL short to CANH CANL and CANH open
Figure 6. ISO Loop Time with Bus Failure
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Figure 7. Test Set Up for Propagation Delay with GND Shift in a 5 Node Configuration
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
TX HIgh: RECESSIVE Bit
TX High: RECESSIVE Bit
VTX
TX Low: DOMINANT Bit
CANL
5.0V 3.6V
CANH
VTH(DR)
1.4V 0.0V 2.2V
VDIFF VRX
VTH(RD)
tOFFTX
-5.0V 0.7VCC
tONRX tOFFRX
0.3VCC
t
RECESSIVE Bit DOMINANT Bit RECESSIVE Bit
Figure 8. Device Signal Waveforms
TPCLK
CS
TLEAD TWCLKH TLAG
SCLK
TWCLKL TSISU TSIH
MOSI
Undefined
TVALID TSOEN
D0
Don't Care
D7
Don't Care
TSODIS
MISO
D0
Don't Care
D7
Figure 9. Timing Characteristic
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Analog Integrated Circuit Device Data Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The MC33889 is an integrated circuit dedicated to automotive applications. It includes the following functions: * One full protected voltage regulator with 200 mA total output current capability. * Driver for external path transistor for V2 regulator function. * Reset, programmable watchdog function * Four operational modes * Wake-up capabilities: Forced wake-up, cyclic sense and wake-up inputs, CAN and the SPI * Can low speed fault tolerant physical interface.
FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RX AND TX)
The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontroller's CAN protocol handler. TX is an input and controls the CANH and CANL line state (dominant when TX is LOW, recessive when TX is HIGH). RX is an output and reports the bus state (RX LOW when CAN bus is dominant, HIGH when CAN bus is recessive).
VOLTAGE SUPPLY (VSUP)
The VSUP pin is the battery supply input of the device.
HIGH-SIDE OUTPUT 1 (HS1)
The HS pin is the internal high-side driver output. It is internally protected against overcurrent and overtemperature.
VOLTAGE REGULATOR ONE (VDD1)
The VDD1 pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130C typical. When the temperature exceeds the overtemperature shutdown (170C typical), the regulator is turned off. VDD1 includes an undervoltage reset circuitry, which sets the RST pin LOW when VDD is below the undervoltage reset threshold.
LEVEL 0-1 INPUTS (L0: L1)
The L0: L1 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by the SPI. These inputs can be used as wakeup events for the SBC when operating in the Sleep or Stop mode.
VOLTAGE REGULATOR TWO (V2)
The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open.
RESET (RST)
The Reset pin RST is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes.
RTH (RTH)
Pin for the connection of the bus termination resistor to CANH
INTERRUPT (INT)
The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10 sec. typical pulse when the device is in Stop mode.
RTL (RTL)
Pin for the connection of the bus termination resistor to CANL
CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL)
The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the state of CANH and CANL is reported through RXD output.
GROUND (GND)
This pin is the ground of the integrated circuit.
SYSTEM CLOCK (SCLK) V2CTRL (V2CTRL)
The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. SCLK is the Serial Data Clock input pin of the serial peripheral interface.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MASTER IN/SLAVE OUT (MISO
MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin.
CHIP SELECT (CS)
CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected.
WATCH DOG (WDOG) MASTER OUT/SLAVE IN (MOSI)
MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
DEVICE SUPPLY The device is supplied from the battery line through the VSUP pin. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5 V and under the jump start condition at 27 V DC. This pin sustains standard automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical, the MC33889 detects it and stores the information in the SPI register, in a bit called "BATFAIL". This detection is available in all operation modes. VDD1 VOLTAGE REGULATOR VDD1 Regulator is a 5.0 V output voltage with total current capability of 200 mA. It includes a voltage monitoring circuitry associated with a reset function. The VDD1 regulator is fully protected against overcurrent, short-circuit and has overtemperature detection warning flags and shutdown with hysteresis. V2 REGULATOR V2 Regulator circuitry is designed to drive an external path transistor in order to increase output current flexibility. Two pins are used: V2 and V2CTRL. Output voltage is 5.0 V and is realized by a tracking function of the VDD1 regulator. A recommended ballast transistor is the MJD32C. Other transistors might be used, however depending upon the PNP gain, an external resistor capacitor network might be connected between the emitter and base of the PNP. The use of external ballast is optional (refer to simplified typical application). The state of V2 is reported into the IOR register (if V2 is below 4.5 V typical, or in cases of overload or shortcircuit). HS1 VBAT SWITCH OUTPUT HS1 output is a 2.0 ohm typical switch from the VSUP pin. It allows the supply of external switches and their associated pullup or pull-down circuitry, for example, in conjunction with the wake-up input pins. Output current is limited to 200 mA and HS1 is protected against short-circuit and has an over temperature shutdown (reported into the IOR register). The HS1 output is controlled from the internal register and the SPI. It can be activated at regular intervals in sleep mode thanks to an internal timer. It can also be permanently turned on in normal or stand-by modes to drive external loads, such as relays or supply peripheral components. In case of inductive load drive, external clamp circuitry must be added. SPI The complete device control as well as the status report is done through an 8 bit SPI interface. Refer to the SPI paragraph. CAN The device incorporates a low speed fault tolerant CAN physical interface. The speed rate is up to 125 kBauds. The state of the CAN interface is programmable through the SPI. Reference the CAN transceiver description on page 30. PACKAGE AND THERMAL CONSIDERATION The device is proposed in a standard surface mount SO28 package. In order to improve the thermal performances of the SO28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board.
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Analog Integrated Circuit Device Data Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTRODUCTION The device has four modes of operation, normal, stand-by, sleep and stop modes. All modes are controlled by the SPI. An additional temporary mode called "normal request mode" is automatically accessed by the device (refer to state machine) after wake-up events. Special mode and configurations are possible for software application debug and flash memory programming. NORMAL MODE In this mode both regulators are ON, and this corresponds to the normal application operation. All functions are available in this mode (watchdog, wake-up input reading through the SPI, HS1 activation, and CAN communication). The software watchdog is running and must be periodically cleared through the SPI. STANDBY MODE Only the Regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2CTRL pin. The CAN cell is not available, as powered from V2. Other functions are available: wake-up input reading through the SPI and HS1 activation. The watchdog is running. SLEEP MODE Regulators 1 and 2 are OFF. In this mode, the MCU is not powered. The device can be awakened internally by cyclic sense via the wake-up input pins and HS1 output, from the forced wake function, the CAN physical interface, and the SPI (CS pin). STOP MODE Regulator 2 is turned OFF by disabling the V2CTRL pin. Regulator 1 is activated in a special low power mode which allows it to deliver 2.0 mA. The objective is to supply the MCU of the application while it is turned into a power saving condition (i.e stop or wait mode). Stop mode is entered through the SPI. Stop mode is dedicated to powering the Microcontroller when it is in low power mode (stop, pseudo stop, wait etc.). In these modes, the MCU supply current is less than 1.0 mA. The MCU can restart its software application very quickly without the complete power up and reset sequence. When the application is in stop mode (both MCU and SBC), the application can wake-up from the SBC side (ex cyclic sense, forced wake-up, CAN message, wake-up inputs) or the MCU side (key wake-up etc.). When Stop mode is selected by the SPI, stop mode becomes active 20 s after end of the SPI message. The "go to stop" instruction must be the last instruction executed by the MCU before going to low power mode. In Stop mode, the Software watchdog can be "running" or "not running" depending on the selection by the SPI. Refer to the SPI description, RCR register bit WDSTOP. If the W/D is enabled, the SBC must wake-up before the W/D time has expired, otherwise a reset is generated. In stop mode, the SBC wake-up capability is identical as in sleep mode. STOP MODE: WAKE-UP FROM SBC SIDE, INT PIN ACTIVATION When an application is in stop mode, it can wake-up from the SBC side. When a wake-up is detected by the SBC (CAN, Wake-up input, forced wake-up, etc.), the SBC turns itself into Normal request mode and activates the VDD1 main regulator. When the main regulator is fully active, then the wake-up is signalled to the MCU through the INT pin. The INT pin is pulled low for 10 s and then returns high. Wake-up events can be read through the SPI registers. STOP MODE: WAKE-UP FROM MCU SIDE When the application is in stop mode, the wake-up event may come to the MCU. In this case, the MCU has to signal to the SBC that it has to go into Normal mode in order for the VDD1 regulator to be able to deliver full current capability. This is done by a low to high transition of the CS pin. The CS pin low to high activation has to be done as soon as possible after the MCU. The SBC generates a pulse at the INT pin. Alternatively the L0 and L1 inputs can also be used as wakeup from the Stop mode. STOP MODE CURRENT MONITORING If the current in Stop mode exceeds the IDD1S-WU threshold, the SBC jumps into Normal request mode, activates the VDD1 main regulator, and generates an interrupt to the MCU. This interrupt is not maskable and a not bit are set into the INT register. SOFTWARE WATCHDOG IN STOP MODE If the watchdog is enabled (register MCR, bit WDSTOP set), the MCU has to wake-up independently of the SBC before the end of the SBC watchdog time. In order to do this, the MCU has to signal the wake-up to the SBC through the SPI wake-up (CS pin low to high transition to activated the SPI wake-up). Then the SBC wakes up and jumps into the normal request mode. The MCU has to configure the SBC to go to either into normal or standby mode. The MCU can then choose to go back into stop mode. If no MCU wake-up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request mode. The MCU can then be initialized.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after a wake-up event from sleep or stop mode, or after device power up. In this mode, the VDD1 regulator is ON, V2 is off, and the reset pin is high. As soon as the device enters the normal request mode, an internal 350 ms timer is started. During these 350 ms, the microcontroller of the application must address the SBC via the SPI and configure the watchdog register (TIM1 register). This is the condition for the SBC to leave the Normal request Mode and enter the Normal mode, and to set the watchdog timer according to the configuration done during the Normal Request mode. The "BATFAIL flag" is a bit which is triggered when VSUP falls below 3.0 V. This bit is set into the MCR register. It is reset by the MCR register read. INTERNAL CLOCK This device has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time etc....). RESET PIN A reset output is available in order to reset the microcontroller. Reset causes are: * VDD1 falling out of range: if VDD1 falls below the reset threshold (parameter RST-TH), the reset pin is pulled low until VDD1 returns to the nominal voltage. * Power on reset: at device power on or at device wake-up from sleep mode, the reset is maintained low until VDD1 is within its operation range. * Watchdog timeout: if the watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset duration time (parameter: RESET-DUR). For debug purposes at 25C, the reset pin can be shorted to 5.0 V. SOFTWARE WATCHDOG (SELECTABLE WINDOW OR TIMEOUT WATCHDOG) The software watchdog is used in the SBC normal and stand-by modes for monitoring the MCU. The watchdog can be either a window or timeout. This is selectable by the SPI (register TIM, bit WDW). Default is the window watchdog. The period of the watchdog is selectable by the SPI from 5.0 to 350 ms (register TIM, bits WDT0 and WDT1). When the window watchdog is selected, the closed window is the first half of the selected period, and the open window is the second half of the period. The watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the closed window will generate a reset. The Watchdog is cleared through the SPI by addressing the TIM register. Refer to "table for reset pin operations" operation in mode 2.
WAKE-UP CAPABILITIES Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake-up has occurred, the wake-up event is stored into the WUR or CAN registers. The MCU can then access the wake-up source. The wake-up options are selectable through the SPI while the device is in normal or standby mode, and prior to entering low power mode (sleep or stop mode). WAKE-UP FROM WAKE-UP INPUTS (L0, L1) WITHOUT CYCLIC SENSE The wake-up lines are dedicated to sense external switch states, and when changes occur to wake-up the MCU (In sleep or stop modes). The wake-up pins are able to handle 40 V DC. The internal threshold is 3.0 V typical, and these inputs can be used as an input port expander. The wake-up inputs state can be read through the SPI (register WUR). L0 has a lower threshold than L1 in order to allow a connection and wake-up from a digital output such as a CAN physical interface. CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER AND WAKE-UP INPUTS L0, L1) The SBC can wake-up from a state change of one of the wake-up input lines (L0, L1), while the external pullup or pulldown resistor of the switches associated to the wake-up input lines are biased with HS1 VSUP switch. The HS1 switch is activated in sleep or stop mode from an internal timer. Cyclic sense and forced wake-up are exclusive. If Cyclic sense is enabled, the forced wake-up can not be enabled. INFO FOR CYCLIC SENSE + DUAL EDGE SELECTION In case the Cyclic sense and Lx both level sensitive conditions are use together, the initial value for Lx inputs are sampled in two cases: 1) When the register LPC[D3 and D0] are set and 2) At cyclic sense event, that is when device is in sleep or stop mode and HS1 is active. The consequence is that when the device wake up by Lx transition, the new value is sampled as default, then when the device is set back into low power again, it will automatically wake up. The user should reset the LPC bits [D3 and D0] to 0 and set them again to the desired value prior to enter sleep or stop mode. FORCED WAKE-UP The SBC can wake-up automatically after a predetermined time spent in sleep or stop mode. Forced wake-up is enabled by setting bit FWU in the LPC register. Cyclic sense and forced wake-up are exclusive. If forced wake-up is enabled, the Cyclic sense can not be enabled.
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CAN WAKE-UP The device can wake-up from a CAN message. A CAN wake-up cannot be disabled. SPI WAKE-UP The device can wake-up by the CS pin in sleep or stop mode. Wake-up is detected by the CS pin transition from a low to high level. In stop mode this correspond to the condition where the MCU and SBC are both in Stop mode, and when the application wake-up events come through the MCU. SYSTEM POWER UP At power up the device automatically wakes up. DEVICE POWER UP, SBC WAKE UP After device or system power up or a wake-up from sleep mode, the SBC enters into "reset mode" then into "normal request mode".
BATTERY FALL EARLY WARNING This function provides an interrupt when the VSUP voltage is below the 6.1 V typical. This interrupt is maskable. A hysteresis is included. Operation is only in Normal and Stand-by modes. VBAT low state reports in the IOR register. RESET AND WDOG OPERATION The following figure shows the reset and watchdog output operations. Reset is active at device power up and wake-up. Reset is activated in case the VDD1 falls or the watchdog is not triggered. The WDOG output is active low as soon as the reset goes low and stays low for as long as the watchdog is not properly re-activated by the SPI. The WDOG output pin is a push pull structure than can drive external components of the application, for instance to signal the MCU is in a wrong operation. Even if it is internally turned on (low-state), the reset pin can be forced to 5.0 V at 25C only, thanks to its internally limited current drive capability. The WDOG stays low until the Watchdog register is properly addressed through the SPI. Watchdog timeout VDD1 RESET WDOG SPI W/D clear SPI CS Watchdog period
Watchdog register addressed Figure 10. Reset and WDOG Function Diagram DEBUG MODE APPLICATION HARDWARE AND SOFTWARE DEBUG WITH THE SBC. When the SBC is mounted on the same printed circuit board as the micro controller, it supplies both application software and the SBC with a dedicated routine that must be debugged. The following features allow the user to debug the software by disabling the SBC internal software watchdog timer. DEVICE POWER UP, RESET PIN CONNECTED TO VDD1 At SBC power up, the VDD1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs every 350 ms. In order to allow software debugging and avoid an MCU reset, the Reset pin can be connected directly to VDD1 by a jumper. DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY DEBUG AND STOP DEBUG) The software watchdog can be disabled through the SPI. In order to avoid unwanted watchdog disables, and to limit the risk of disabling the watchdog during an SBC normal operation, the watchdog disable has to be performed with the following sequence: Step 1) Power down the SBC Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode) Step 3) Write to the TIM1 register to allow the SBC to enter Normal mode Step 4) Write to the MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000)
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Step 5) Write to the MCR register normal debug (0001 x101), stand-by debug (0001 x110), or Stop debug (0001 x111) While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and hardware debugging.
Step 6) To leave the debug mode, write 0000 to the MCR register. To avoid entering the debug mode after a power up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR. Figure 11 illustrates entering the debug mode.
VSUP VDD1 BATFAIL
TIM1(step 3) SPI
MCR (step5) SPI: read batfail
MCR (step6)
MCR(step4) debug mode
SBC in debug Mode, no W/D
SBC not in debug Mode and W/D on
Figure 11. Debug Mode Enter MCU FLASH PROGRAMMING CONFIGURATION To facilitate the possibility of down loading software into the application memory (MCU EEPROM or Flash), the SBC allows the following capabilities: The VDD1 can be forced by an external power supply to 5.0 V and the reset and WDOG output by external signal sources to zero or 5.0 V without damage. This supplies the complete application board with external power supply and applies the correct signal to the reset pin.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
CAN TRANSCEIVER DESCRIPTION
Vsup
VSE-H (1.85V) CANH
V2
Driver
CANL
IcanHpd
SH
CANH RTL RTH RtH RtL
SL
VSE-L (3.05V)
Stvbat
SRL
RXD Rx multiplexer Vdiff
SRH
V2
Failure detection
IcanLpu
CANL
V2
TXD Tx driver
Driver
Vwake-H (2V) CANH
SPI
CAN mode control
Hwake
CANL
GND
Lwake
Vwake-L (3V)
Figure 12. Simplified Block Diagram of the CAN Transceiver of the MC33889 General description CAN driver: The CANH driver is a "high side" switch to the V2 voltage (5V). The CANL driver is a "low side" switch to gnd.The turn on and turn off time is controlled in order to control the slew rate, and the CANH and CANL driver have a current limitation as well as an over temperature shutdown. The CAN H or CANL driver can be disabled in case a failure is detected on the CAN bus (ex: CANH driver is disabled in case CANH is shorted to VDD). The disabling of one of the drivers is controlled by the CAN logic and the communication continues via the other drivers. When the failure is removed the logic detects a failure recovery and automatically reenables the associated driver. The CAN drivers are also disabled in case of a Tx failure detection. Bus termination: The bus is terminated by pull up and pull down resistors, which are connected to GND, VDD or VBAT through dedicated RTL and RTH pins and internal switches Srh, Srl, Stvbat. Each node must have a resistor connected between CANH and RTH and between CANL and RTL. The resistor value should be between 500 and 16000 ohms. Transmitter Function CAN bus levels are called Dominant and Recessive, and correspond respectively to Low and High states of the TX input pin. Dominant state: The CANH and CANL drivers are on. The voltage at CANL is <1.4V, the voltage at CANH is >3.6V, and the differential voltage between CANH and CANL line is >2.2V (3.6V-1.4V). Recessive state: This is a weak state, where the CANH and CANL drivers are off. The CANL line is pulled up to 5V via the RTL pin and RTL resistor, and the CANH line is pull down via the RTH and RTH resistor. The resultant voltage at CANL is 5V and 0V at CANH. The differential voltage is -5V (0V - 5V). The recessive state can be over written by any other node forcing a Dominant state.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Receiver Function In normal operation (no bus failures), RX is the image of the differential bus voltage. The differential receiver inputs are connected to CANH and CANL. The device incorporates single ended comparators connected to CANH and CANL in order to monitor the bus state as well as detect bus failures. Failures are reported via the SPI. In normal operation when no failure is present, the differential comparator is active. Under a fault condition, one of the two CANH or CANL pins can be become nonoperational. The single ended comparator of either CANH or CANL is activated and continues to report a bus state to Rx pin. The device permanently monitors the bus failure and recovery, and as soon as fault disappears, it automatically switches back to differential operation. CAN interface operation Mode The CAN has 3 operation modes: TxRx (TransmitReceive), Receive Only, and Term-VBAT (Terminated to VBAT). The mode is selected by the SPI. As soon as the MC33889 mode is sleep or stop (selected via MCR register), the CAN interface automatically enters Tem-Vbat mode. Tx Rx mode: In this mode, the CAN drivers and receivers are enabled, and the device is able to send and receive messages. Bus failures are detected and managed, this means that in case of a bus failure, one of the CAN drivers can be disabled, but communication continues via the remaining drivers. Receive Only mode: In this mode, the transmitter path is disabled, so the device does not drive the bus. It maintains CANL and CANH in the recessive state. The receiver function operates normally. TermVbat mode: In this mode, the transmitter and receiver functions are disabled. The CANL pin is connected to VSUP through the
RTL resistor and internal pull up resistor of 12.5kOhms. In this mode, the device monitors the bus activity and if a wake up conditions is encountered on the CAN bus, it will wakes up the MC33889. The device will enter into a normal request mode if low power mode was in sleep, or generates an INT. It enters into Normal request mode if low power mode was in stop mode. If the device was in normal or stand by mode, the Rx pin will report a wake up (feature not available on the MC33889B). See Rx pin behavior. Bus Failure Detection General description: The device permanently monitors the bus lines and detects faults in normal and receive only modes. When a fault is detected, the device automatically takes appropriate actions to minimize the system current consumption and to allow communication on the network. Depending on the type of fault, the mode of operation, and the fault detected, the device automatically switches off one or more of the following functions: CANL or CANH line driver, RTL or RTH termination resistors, or internal switches. These actions are detailed in the following table. The device permanently monitors the faults and in case of fault recovery, it automatically switches back to normal operation and reconnects the open functions. Fault detection and recovery circuitry have internal filters and delays timing, detailed in the AC characteristics parameters. The failure list identification and the consequence on the device operation are described in following table. The failure detection, and recovery principle, the transceiver state after a failure detected, timing for failure detection and recovery can be found in the ISO11898-3 standard. The following table is a summary of the failure identifications and of the consequences on the CAN driver and receiver when the CAN is in Tx Rx mode.
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Bus failure identification
Description
Consequence on CAN driver
Consequence on Rx pin
no failure
default operation: CAN H and CANL driver active, RTH and RTL termination switched ON default operation default operation CANH driver turn OFF. RTH termination switched OFF CANH driver turn OFF. RTH termination switched OFF default operation CANL driver is OFF. RTL termination switched OFF CANL driver is ON. RTL termination active CANL driver is OFF. RTL termination switched OFF
default operation: Report differential receiver output default operation default operation Rx report CANL single ended receiver
1 5 8, 3a
CANH open wire CANH shorted to gnd CANH shorted to Vdd (5V) CANH shorted to Vbat
3
Rx report CANL single ended receiver
2 4, 7
CANL open wire CANL shorted to gnd or CANL shorted to CANH CANL shorted to Vdd (5V) CANL shorted to Vbat
default operation Rx report CANH single ended receiver
9 6
default operation Rx report CANH single ended receiver
Open wire detection operation: Description: The CANH and CANL open wire failures are not described in the ISO document. Open wire is only diagnostic information, as no CAN driver or receiver state will change in case of an open wire condition. In case one of the CAN wires are open, the communication will continue through the remaining wire. In this situation the
MC33889 will receive information on one wire only and the consequences are as follows: when the bus is set in dominant: - The differential receiver will toggle - Only one of the single ended receivers CANH or of CANL will toggle The following figure illustrates the CAN signal during normal communication and in the example of a CANH open wire. The single ended receiver is sampled at the differential receiver switching event, in a window of 1s.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
(No open wire, or open wire recovery) Rec CANL CANH Dom Rec
(CAN H open wire) Rec CANL CANH Dom Rec
Sampling point -3.2V Diff S-L S-H 1us Sampling dominant level = > no failure or "recovery pulse" -3.2V Diff S-L S-H
Sampling point
Sampling recessive level = > open wire "detection pulse"
Figure 13. CAN Normal Signal Communication and CAN Open Wire
S-H CANH Diff CANL S-L
1us
Sampling
Dom Rec
1us
Sampling
CANH counter
L-counter +/(count = 4) L-open (count = 0) recover
Figure 14. Open Wire Detection Principle Open wire detection, MC33889B and D: Failure detection: The device will detect a difference in toggling counts between the differential receiver and one of the single ended receivers. Every time a difference in count is detected a counter is incremented. When the counter reaches 4, the device detects and reports an open wire condition. The open Open wire recovery: When the open wire failure has recovered, the difference in count is reduced and the device detects the open wire recovery. MC33889B: When detection is complete, the counter is no longer incremented. It can only be decremented by sampling of the dominant level on the S-H (S-L) (recovery pulse). When it reaches zero, the failure has recovered.
wire detection is performed only when the device receives a message and not when it send message.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
In application, with CAN communication, a recovery condition is detected after 4 acknowledge bits are sent by the MC33889B. MC33889D: When detection is complete, the counter is decremented by sampling the dominant pulse (recovery pulse) on S-H (SL), and incremented (up to 4) by sampling the recessive pulse (detection pulses) on S-H (S-L). It is necessary to get 4 consecutive dominant samples (recovery pulse) to get to zero. When reaching zero, the failure is recovered. In application with real CAN communication, a recovery condition will not be detected by a single acknowledge bit send by MC33889D, but requires a complete CAN message (at least 4 dominant bits) send in dual wire mode, without reception of any bit in single wire mode. Tx permanent dominant detection: In addition to the previous list, the MC33889 detects a permanent low state at the TX input which results in a
permanent dominant bus state. If TX is low for more than 0.75-4ms, the bus output driver is disabled. This avoids blocking communication between other nodes of the network. TXD is reported via the SPI (RCR register bit D1: TXFAILURE). Tx permanent dominant recovery is done with TX recessive for more than typ 32us. Rx pin behavior while CAN interface is in TermVbat. The MC33889D is able to signal bus activity on Rx while the CAN interface is in TermVbat and the SBC in normal or standby mode. When the bus is driven into a dominant state by another sending node, each dominant state is reported at Rx by a low level, after a delay of TWAKE. The bus state report is done through the CAN interface wake up comparator on CANL and CANH, and thus operates also in case of bus failure. This is illustrated in the following figure.
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Other CAN node send
CANL terminated to Vbat Recessive state Recessive state
CANL CANH
Dominant state
Dominant state
Rx
TWAKE TWAKE
CAN in TermVbat CAN in TxRx MC33889D in Normal mode MC33889D in Normal mode, Standby mode or in stop mode
CAN in TxRx MC33889D in Normal mode
TWAKE: duration of the CAN wake up filter, typ 16s. The MC33889D Rx dominant low level duration is the difference between the duration of the bus minus the Twake, as illustrated below (Trx_dom = Tbus_dom - Twake)
Tx sender node Example: A dominant duration at the bus level of 5 bits of 8us each results in a 40us bus dominant. This results in a 24s (40s-16s) dominant level at Rx of MC33889D (while the CAN of the MC33889D is in TermVbat). Tx MC33889D Rx MC33889D
TWAKE
Dominant state
TRX_DOM TBUS_DOM
Figure 15. Bus State Report of the CAN Interface Wake-Up Comparator on CANL and CANH
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
The following table summarizes the device behavior when a CAN Wake Up event occurs. Table 6. Summary of RX Pin Operations for Wake up Signaling
SBC mode Normal Standby Sleep CAN state TermVbat TermVbat TermVbat MC33889B no event on RX, no bit set no event on RX, no bit set SBC mode transition to Normal request, bit CANWU set INT pulse, bit CANWU set MC33889D RX pulse (1), bit CANWU is not set RX pulse (1), bit CANWU is not set SBC mode transition to Normal request, bit CANWU set Int pulse, bit CANWU set
Stop
TermVbat
Notes 29. pulse duration is bus dominant duration minus Twake.
GND SHIFT DETECTION GENERAL When normally working in two-wire operating mode, the CAN transmission can afford some ground shift between different nodes without trouble. Should a bus failure occur, the transceiver switches to single-wire operation, therefore working with less noise margin. The affordable ground shift is decreased. The SBC provides a ground shift detection for diagnosis purpose. The four ground shift levels are selectable and the detection is stored in the IOR register which is accessible via the SPI. Table 7. 33889 Table of Operations The table below describe the SBC operation modes.
MODE Normal Request VOLTAGE REGULATOR HS1 SWITCH VDD1: ON V2: OFF HS1: OFF Normal VDD1: ON V2: ON HS1 controllable WAKE-UP CAPABILITIES (IF ENABLED)
DETECTION PRINCIPLE The gnd shift to detect is selected via the SPI from 4 different values (-0.3 V, -0.7 V, -1.2 V, -1.7 V). At each TX falling edge (end of recessive state), the CANH voltage is sensed. If it is detected to be below the selected gnd shift threshold, the bit SHIFT is set at 1 in the IOR register. No filter is implemented. Required filtering for reliable detection should be done by software (e.g. several trials).
DEVICE STATE DESCRIPTION
RESET PIN Low for 1ms, then high
INT
SOFTWARE CAN CELL WATCHDOG term Vbat
Normally high. Active low if W/D or VDD1 under voltage occur Normally high. Active low if W/D or VDD1 under voltage occur CAN (always enable) SPI and L0,L1 Cyclic sense or Forced Wake-up
If enabled, signal failure (VDD pre warning temp, CAN, HS1) If enabled, signal failure (VDD temp, HS1)
Running
Term Vbat Tx/Rx Rec only
Standby
VDD1: ON V2: OFF HS1 controllable
Running
Term Vbat Tx/Rx Rec only Term Vbat.
Stop
VDD1: ON (limited current capability) V2: OFF HS1: OFF or cyclic
Normally high. Signal SBC - Running if Active low if W/D wake-up enabled or VDD1 under (not maskable) - Not Running voltage occur if disabled
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Table 7. 33889 Table of Operations The table below describe the SBC operation modes.
MODE Sleep VOLTAGE REGULATOR HS1 SWITCH VDD1: OFF V2: OFF HS1 OFF or cyclic WAKE-UP CAPABILITIES (IF ENABLED) CAN (always enable SPI and L0,L1 Cyclic sense Forced Wake-up RESET PIN Low INT Not active SOFTWARE CAN CELL WATCHDOG No Running Term Vbat.
State Machine (not valid in debug modes)
W/D: timeout OR VDD1 low W/D: timeout & Nostop & !BATFAIL Reset counter (1 ms) expired 2 SPI: standby & W/D trigger (note1) 3
1
Reset
W /D :t im
Normal Request
1 VDD1 low OR W/D: time out 350 ms & !Nostop
eo ut O R
Standby
Nostop & SPI: sleep & CS low to high transition Nostop & SPI: sleep & CS low to high transition
SBC power up
S hi PI: gh S tra top ns & iti CS on
lo w
to
4
SPI: standby 1
VD D1
lo
w
(n
Power Down
ot
e2
)
2 1
Stop
W/D: timeout OR VDD1 low
SPI: Stop & CS low to high transition
Normal
Wake-up (VDD1 high temperature OR (VDDd1 low > 100 ms & VSUP >BFew)) & Nostop & !BATFAIL
SPI: normal
Wake-up
W /D rig :T r ge
Sleep
1
2
3
4
denotes priority "W/D: timeout" means TIM1 register not written before W/D timeout period expired, or W/D written in incorrect time window if window W/D selected (except stop mode). In normal request mode timeout is 355 ms p2.2 (350 ms p3)ms. "SPI: Sleep" means SPI write command to MCR register, data sleep "SPI: Stop" means SPI write command to MCR register, data stop "SPI: Normal" means SPI write command to MCR register, data normal "SPI: Standby" means SPI write command to MCR register, data standby Note 1: these 2 SPI commands must be send in this sequence and consecutively. Note 2: if W/D activated
State machine description: "Nostop" means Nostop bit = 1 "! Nostop" means Nostop bit = 0 "BATFAIL" means Batfail bit = 1 "! BATFAIL" means Batfail bit = 0 "VDD1 over temperature" means VDD1 thermal shutdown occurs "VDD1 low" means VDD1 below reset threshold "VDD1 low > 100 ms" means VDD1 below reset threshold for more than 100 ms "W/D: Trigger" means TIM1 register write operation. VSUP > BFew means VSUP > Battery Fall Early Warning (6.1 V typical)
Figure 16. Simplified State Machine
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Behavior at SBC power up
Figure 17. Behavior at SBC Power Up Transitions to enter debug modes
W/D: timeout 350 ms
Normal Request
W/D: Trigger
Reset counter (1.0 ms) expired
Reset
Power Down
Normal
SPI: MCR (0000) & Normal Debug
Normal Debug
SPI: MCR (0000) & Standby Debug
Standby Debug
Figure 18. Transitions to Enter Debug Modes
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
Simplified State machine in debug modes
W/D: timeout 350ms
Stop (1)
Wake-up
Normal Request
SPI: standby & W/D: Trigger R
Reset counter (1ms) expired
Reset
Wake-up
Sleep
& !BATFAILNOSTOP & SPI: Sleep
R
W/ D:
Trig ger
R
R
R
SPI: Stop
SPI: standby debug
ug
E
SP
I: St an
eb
E
SPI: Standby debug
Standby Debug
SPI: Normal debug
Normal Debug
R
R
(1) If stop mode entered, it is entered without watchdog, no matter the WDSTOP bit. (E) debug mode entry point (step 5 of the debug mode entering sequence). (R) represents transitions to reset mode due to Vdd1 low.
Figure 19. Simplified State Machine in Debug Mode
SPI: Normal Debug
ld
db
y
or
ma
D eb
ug
Standby
SP I: n
Normal
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS SPI INTERFACE
Bit7 MISO A2
Bit6 A1
Bit5 A0
Bit4 R/W
Bit3 D3
Bit2 D2
Bit1 D1
Bit0 D0 MOSI Read operation: R/W bit = 0 Write operation: R/W bit = 1
address
data
Figure 20. Data Format Description The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register address, bit 4 is a read/write bit. The last 4 bits are data send from MCU to SBC or read back from SBC to MCU. During write operation state of MISO has no signification. During read operation only the last 4 bits at MISO have a meaning (content of the accessed register) Following tables describe the SPI register list, and register bit meaning. Registers "reset value" is also described, as well as the "reset condition". reset condition is the condition which cause the bit to be set at the "reset value". Possible reset condition are: Power On Reset: POR SBC mode transition: NR2R - Normal Request to Reset mode NR2N - Normal Request to Normal mode N2R - Normal to Reset mode STB2R - Standby to Reset mode STO2R - Stop to Reset mode SBC mode:RESET - SBC in Reset mode
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 8. List of Registers Name MCR Address $0 0 0 Description Mode control register Comment and usage Write: Control of normal, standby, sleep, and stop modes Read: BATFAIL flag and other status bits and flags Write: Configuration of reset voltage level, WD in stop mode, low power mode selection Read: CAN wake-up event, Tx permanent dominant Write: CAN module control: TX/RX, Rec only, term VBAT, Normal and extended modes, filter at L0 input. Read: CAN failure status bits Write: HS1 (high-side switch) control in normal and standby mode. Gnd shift register level selection Read: HS1 over temp bit, SHIFT bit (gnd shift above selection), VSUP below 6.1V, V2 below 4.0 V Write: Control of wake-up input polarity Read: Wake-up input, and real time LX input state Write: TIM1, Watchdog timing control, window or Timeout mode. Write: TIM2, Cyclic sense and force wake-up timing selection Write: HS1 periodic activation in sleep and stop modes Force wake-up control Write: Interrupt source configuration Read: INT source
RCR
$0 0 1
Reset control register
CAN
$0 1 0
CAN control register
IOR
$0 1 1
I/O control register
WUR TIM LPC INTR
$1 0 0 $1 0 1 $1 1 0 $1 1 1
Wake-up input register Timing register Low power mode control register Interrupt register
Register description Table 9. MCR Register
MCR $000b W R Reset Reset condition BATFAIL 0 D3 D2 MCTR2 VDDTEMP 0 POR, RESET D1 MCTR1 GFAIL 0 POR, RESET D0 MCTR0 WDRST 0 POR, RESET
Table 10. Control bits
MCTR2 0 MCTR1 0 MCTR0 0 SBC MODE Enter/leave debug mode DESCRIPTION To enter debug mode, SBC must be in Normal or Standby mode and BATFAIL(1) must be still at 1. To leave debug mode, BATFAIL must be at 0.
0 0 0
0 1 1
1 0 1
Normal Standby Stop, watchdog off (2)
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
MCTR2 0 1 1 1
MCTR1 1 0 0 1
MCTR0 1 0 1 0
SBC MODE Stop, watchdog on (2) Sleep (3) Normal Standby
DESCRIPTION
No watchdog running, debug mode
1
1
1
Stop (4)
(1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when VSUP falls below 3V. (2): Watchdog ON or OFF depends on the RCR register bit D3. (3): Before entering sleep mode, bit NOSTOP in RCR register must be previously set to 1. (4): Stop command should be replaced by Stop Watchdog OFF. MCTR2=0, MCTR1= MCTR0=1 Table 11. Status bits
STATUS BIT DESCRIPTION
GFAIL BATFAIL VDDTEMP WDRST Table 12. RCR register
RCR $001b W R Reset Reset condition 1 POR, RESET D3 WDSTOP
Logic OR of CAN failure, HS1 failure, V2LOW Battery fail flag (VSUP<3V) Temperature pre-warning on VDD (latched) Watchdog reset occurred
D2 NOSTOP
D1
D0 RSTTH
TXFAILURE 0 POR, NR2N
CANWU 0 POR
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 13. Control bits
Status bit WDSTOP Bit value 0 1 NOSTOP 0 1 RSTTH 0 1 CANWU TXFAILURE 1 1 Description No watchdog in stop mode Watchdog runs in stop mode Stop mode is default low power mode Sleep mode is default low power mode Reset threshold 1 selected (typ 4.6V) Reset threshold 2 selected (typ 4.2V) Wake-rom CAN Tx permanent dominant (CAN)
Table 14. CAN register Some description.
CAN $010b W R Reset Reset condition D3 FDIS CS3 0 POR, CAN D2 CEXT CS2 0 POR, CAN D1 CCTR1 CS1 0 POR, CAN D0 CCTR0 CS0 0 POR, CAN
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Fault tolerant CAN transceiver standard modes The CAN transceiver standard mode can be programmed by setting CEXT to 0. The transceiver cell will then be behave as known from MC33388. Table 15. CAN Transceiver Modes
CEXT 0 0 0 0 CCTR1 0 0 1 1 CCTR0 0 1 0 1 RxOnly RxTx Mode TermVBAT
Table 16. CAN transceiver extended modes (CAN with CEXT bit =1 is not recommended)
CEXT (1) 1 1 1 1 CCTR1 0 0 1 1 CCTR0 0 1 0 1 Mode TermVBAT TermVDD RxOnly RxTx
Fault tolerant CAN transceiver extended modes By setting CEXT to 1 the transceiver cell supports sub bus communication Note1: CEXT Bit should be set at 0. The CAN operation in extended mode is not recommended.
FDIS 0 1 L0 wake input filter (20 s typical) Enable (LO wake threshold selectable by WUR register) Disable (L0 wake-up threshold is low level only, no matter D0 and D1 bits set in WUR register).
Note: if DFIS bit is set to 1, WUR register must be read before going into sleep or stop mode in order to clear the wake-up flag. During read out L0 must be at high level and should stay high when entering sleep or stop.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 17. Status bits
CS3 0 0 0 0 0 1 1 1 1 CS2 0 0 1 1 1 0 1 1 1 CS1 0 0 0 1 1 0 0 1 1 CS0 0 1 1 0 1 1 1 0 1 1 5 8, 3a 3 2 4, 7 9 6 CANL open wire CANL short circuit to ground / CANH VDD VBAT Bus failure # no failure CANH open wire CANH short circuit to ground VDD VBAT Description
Comments: CS2 bit at 0 = open failure. CS2 bit at 1 = short failure. (CS3 bit at 0 and (CS1 = 1 or CS2 =1)) = CANH failure. CS3 bit at 1 = CANL failure. CS1 and CS0 bits: short type failure coding (gnd, VDD or VBAT). In case of multiple failures, the last failure is reported.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 18. IOR register.
IOR $011b W R Reset Reset condition SHIFT D3 D2 HS1ON HS1OT 0 POR, RESET D1 GSLR1 V2LOW 0 POR, RESET D0 GSLR0 VSUPLOW 0 POR, RESET
Table 19. Control bits
HS1ON 0 1 HS1 HS1 switch turn OFF HS1 switch turn ON
Table 20. Gnd shift selection
GSLR1 0 0 1 1 GSLR0 0 1 0 1 Typical gnd shift comparator level -0.3 V -0.7 V -1.2 V -1.7 V
Shift 0 1
State Gnd shift value is lower than the level selected by the GSLR1 and GSLR2 bit Gnd shift value is higher than the level selected by the GSLR1 and GSLR2 bit
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 21. Status bits
Status bit HS1OT (*) SHIFT V2LOW VSUPLOW Description High-side 1 over temperature gnd shift level selected by GSLR1 and GSLR2 bits is reached V2 below 4.0 V typical VSUP below 6.1 V typical
(*) Once the HS1 switch has been turned off because of over temperature, it can be turned on again by setting the appropriate control bit to "1".
WUR REGISTER
The local wake-up inputs L0 and L1 can be used in both normal and standby mode as port expander and for waking up the SBC in sleep or stop mode. Table 22. WUR Register
WUR $100b W R Reset Reset condition D3 LCTR3 L1WUb 1 D2 LCTR2 L1WUa 1 D1 LCTR1 L0WUb 1 D0
LCTR0 L0WUa 1
POR, NR2R, N2R, STB2R, STO2R
Table 23. Control bits:.
LCTR3 X X X X 0 0 1 1 LCTR2 X X X X 0 1 0 1 LCTR1 0 0 1 1 X X X X LCTR0 0 1 0 1 X X X X L0 configuration inputs disabled high level sensitive low level sensitive both level sensitive inputs disabled high level sensitive low level sensitive both level sensitive L1 configuration
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 24. Status bits
FDIS bit in CAN register 0
L0WUb
L0WUa
Description
0
0
No wake-up occurred at L0 (sleep or stop mode). Low level state on L0 (standby or normal mode)
1
1
0
Wake-up occurred at L0 (sleep or stop mode). High level state on L0 (standby or normal mode)
0
1
1
Wake-up occurred at L0 (sleep or stop mode with L0 filter disable). WUR must be set to xx00 before sleep or stop mode.
L1WUb 0
L1WUa 0
Description No wake-up occurred at L1 (sleep or stop mode). Low level state on L1 (standby or normal mode)
1
1
Wake-up occurred at L1 (sleep or stop mode). High level state on L1 (standby or normal mode)
TIM REGISTERS
Description: This register is split into 2 sub registers, TIM1 and TIM2. TIM1 controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0. TIM2 is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is 1. No read operation is allowed for registers TIM1 and TIM2
TIM REGISTER
Table 25. TIM Register.
TIM1 $101b W R Reset Reset condition 0 POR, RESET 0 POR, RESET 0 POR, RESET D3 0 D2 WDW D1 WDT1 D0 WDT0
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 26. Watch dog
WDW 0 0 0 0 1 1 1 1 WDT1 0 0 1 1 0 0 1 1 WDT0 0 1 0 1 0 1 0 1 Watchdog timing [ms] 10 50 100 350 10 50 100 350 window watchdog enabled (window lenght is half the watchdog timing) no window watchdog
Table 27. jWatchdog operation (window and timeout) window closed window open for watchdog clear no watchdog clear
window open for watchdog clear
WD timing * 50%
WD timing * 50% Watchdog period (WD timing selected by TIM 1, bit WDW=0) Timeout watchdog
Watchdog period (WD timing selected by TIM 1 bit WDW=1) Window watchdog
TIM2 REGISTER
The purpose of TIM2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching on or off HS1 Table 28. TIM2 Register
TIM2 $101b W R Reset Reset condition 0 POR, RESET 0 POR, RESET 0 POR, RESET D3 1 D2 CSP2 D1 CSP1 D0 CSP0
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 29. Cyclic Sense Timing CSP2 0 0 0 0 1 1 1 1 CSP1 0 0 1 1 0 0 1 1 CSP0 0 1 0 1 0 1 0 1 Cyclic sense timing [ms] 5 10 20 40 75 100 200 400
Cyclic sense on time
Cyclic sense timing 10 s to 20 s HS1 Sample t
LPC REGISTER
Description: This register controls: - The state of HS1 in stop and sleep mode (HS1 permanently off or HS1 cyclic) - Enable or Disable the forced wake-up function (SBC automatic wake-up after time spend in sleep or stop mode, time defined by TIM2 register) - Enable or disable the sense of the wake-up inputs (LX) at sampling point of the cyclic sense period (LX2HS1 bit). Table 30. LPC Register
LPC $110b W R Reset Reset condition 0 POR, NR2R, N2R, STB2R, STO2R 0 POR, NR2R, N2R, STB2R, STO2R 0 POR, NR2R, N2R, STB2R, STO2R 0 POR, NR2R, N2R, STB2R, STO2R D3 LX2HS1 D2 FWU D1 IDDS D0 HS1AUTO
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LX2HS1 X X 0 1
HS1AUTO 0 1 X X
Wake-up inputs supplied by HS1
Autotiming HS1 off On, HS1 cyclic, period defined in TIM2 register
no Yes, LX inputs sensed at sampling point
Bit FWU
Description If this bit is set, and the SBC is turned into sleep or stop mode, the SBC wakes up after the time selected in the TIM2 register Bit = 0: IDDS-WU1 selected (lowest value, typ 3.5mA) Bit = 1: IDDS-WU2 selected (highest value, typ 14mA)
IDDS
Table 31. INTR register
INTR $111b W R Reset Reset condition D3 VSUPLOW VSUPLOW 0 POR, RESET D2 HS1OT-V2LOW HS1OT 0 POR, RESET D1 VDDTEMP VDDTEMP 0 POR, RESET D0 CANF CANF 0 POR, RESET
Table 32. Control bits:
Control bit CANF VDDTEMP HS1OT-V2LOW VSUPLOW Description Mask bit for CAN failures (OR of any CAN failure) Mask bit for VDD medium temperature Mask bit for HS1 over temperature OR V2 below 4V Mask bit for SUP below 6.1V
When the mask bit has been set, INT pin goes low if the appropriate condition occurs.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 33. Status bits:
Status bit CANF VDDTEMP HS1OT VSUPLOW Description CAN failure VDD medium temperature HS1 over temperature VSUP below 6.1V typical
Notes: Bit D2 = 1: INT source is HS1OT If HS1OT-V2LOW interrupt is only selected (only bit D2 set Bit D2 = 0: INT source is V2LOW. in INTR register), reading INTR register bit D2 leads to two possibilities: Upon a wake-up condition from stop mode due to over current detection (IDD1S-WU1 or IDD1S-WU2), an INT pulse is generated, however INTR register contain remains at 0000 (not bit set into the INTR register).
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Q1 RB VBAT V2CTRL V2
5V
VSUP
VSUP monitor CAN supply Dual Voltage Regulator 5V/200mA VDD1 Monitor Mode control
HS1 control
VDD1
5V/200mA
HS1
L0 L1
Oscillator
Programmable wake-up input
Interrupt Watchdog Reset
INT WDOG RESET MOSI SCLK MISO CS V2 TXD RXD GND
SPI Interface
RRTH RTH CANH CANL RRTL RTL Low Speed Fault Tolerant CAN Physical Interface
Figure 21. 33889D/33889B Simplified Typical Application with Ballast Transistor
5V/100mA
VBAT V2CTRL (open) VSUP V2
VSUP Monitor Dual Voltage Regulator VDD1 Monitor
HS1 Control
CAN supply
5V/200mA
VDD1 5V/100mA
Mode Control
HS1
Oscillator
Programmable wake-up input
L0 L1
Interrupt Watchdog Reset
INT WDOG RESET MOSI SCLK MISO CS V2 TX RX GND
SPI Interface
RRTH RTH CANH CANL RRTL RTL Low Speed Fault Tolerant CAN Physical Interface
Figure 22. 33889D/33889B Simplified Typical Application without Ballast Transistor
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A number listed below.
DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B ISSUE G
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PACKAGING PACKAGE DIMENSIONS
DW SUFFIX EG SUFFIX (PB-FREE) 28-PIN PLASTIC PACKAGE 98ASB42345B ISSUE G
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0)
Introduction This thermal addendum is provided as a supplement to the MC33889 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations The MC33889 is offered in a 28 pin SOICW, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RJA). TJ RJA
.
33889
28-PIN SOICW
=
P
DWB SUFFIX 98ASB42345 28-PIN SOICW
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an applicationspecific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 34. Thermal Performance Comparison
Thermal Resistance JA (1) (2) JB JA
(2) (3) (1) (4)
Note For package dimensions, refer to the 33889 device datasheet.
[C/W] 42 11 69 23
(5)
Notes 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3. 5. Thermal resistance between the die junction and the package top surface; cold plate attached to the package top surface and remaining surfaces insulated.
20 Terminal SOICW 1.27 mm Pitch 18.0 mm x 7.5 mm Body
Figure 23. Surface Mount for SOIC Wide Body Non-Exposed Pad
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
RX TX VDD1 RST INT GND GND GND GND V2CTRL VSUP HS1 L0 L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
WDOG CS MOSI MISO SCLK GND GND GND GND CANL CANH RTL RTH V2
A
33889DWB Pin Connections 28-Pin SOICW 1.27 mm Pitch 18.0 mm x 7.5 mm Body
Figure 24. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 35. Thermal Resistance Performance
Thermal Resistance JA Area A (mm2) 0 300 600 (C/W) 69 53 48
Outline:
Area A: Ambient Conditions:
JA .
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
80
Thermal Resistance [C/W]
70 60 50 40 30 20 10 0
x JA
0
300 Heat spreading area A [mm]
600
Figure 25. Device on Thermal Test Board RJA
100 Thermal Resistance [C/W]
10
x JA
1
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s]
Figure 26. Transient Pin Resistance JA Device on Thermal Test Board Area A = 600 (mm2)
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REVISION HISTORY
REVISION HISTORY
REVISION 7.0
DATE 5/2006
DESCRIPTION OF CHANGES
8.0 9.0 10.0
6/2002 8/2006 9/2006
* * * * * * * * * * * * *
11.0
12/2006
Implemented Revision History page Added "EG" PB-Free package type Removed MC33889DW version, and added MC33889B and MC33889D versions Converted to the Freescale format, and updated to the prevailing form and style Modified Device Variations Between the 33889D and 33889B Versions (1) on page 2 Added Thermal Addendum (rev 1.0) on page 56 Changed the Maximum Ratings on page 6 to the standard format Added CAN transceiver description section Corrected two instances where pin LO had an overline, and one instance where pin WDOG did not. Removed MC33889BEG/R2 and MC33889DEG/R2 and replaced them with MCZ33889BEG/R2 and MCZ33889DEG/R2 in the Ondering Information block Replaced the label Logic Inputs with Logic Signals (RX, TX, MOSI, MISO, CS, SCLK, RST, WDOG, INT) on page 6 Changed CS to CS at various places in the document Made changes to Supply Current in Stand-by Mode (7),(9) on page 8 and Supply Current in Normal Mode (7) on page 8
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MC33889 Rev. 11.0 12/2006

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